| VLSI001 |
Dual-Quality 4:2 Compressors For Utilizing In Dynamic Accuracy Configurable Multipliers. |
Abstract |
| VLSI002 |
Multipliers-Driven Perturbation Of Coefficients For Low-Power Operation In Reconfigurable Fir Filters. |
Abstract |
| VLSI003 |
Roba Multiplier: A Rounding-Based Approximate Multiplier For High-Speed Yet Energy-Efficient Digital Signal Processing. |
Abstract |
| VLSI004 |
Design Of Efficient BCD Adders In Quantum-Dot Cellular Automata. |
Abstract |
| VLSI005 |
Power Delay Product Optimized Hybrid Full Adder Circuits. |
Abstract |
| VLSI006 |
Analysis Of Vedic Multiplier Using Various Adder Topologies. |
Abstract |
| VLSI007 |
Design Of Low-Power High-Performance 2–4 And 4–16 Mixed-Logic Line Decoders. |
Abstract |
| VLSI008 |
Fm0 And Manchester Encoding Using Sols Technique With Clock Gating & Power Gating Methods. |
Abstract |
| VLSI009 |
Reconfigurable Delay Optimized Carry Select Adder VLSI Design For Convolutive Blind Source Separation. |
Abstract |
| VLSI010 |
Reconfigurable Constant Multiplication For Fpgas. |
Abstract |
| VLSI011 |
Design Of Power And Area Efficient Approximate Multipliers. |
Abstract |
| VLSI012 |
Multipliers-Driven Perturbation Of Coefficients For Low-Power Operation In Reconfigurable FIR Filters. |
Abstract |
| VLSI013 |
A Computationally Efficient Reconfigurable Constant Multiplication Architecture Based On CSD Decoded Vertical–Horizontal Common Sub-Expression Elimination Algorithm. |
Abstract |
| VLSI014 |
Design Of Low Power 8-Bit Carry Select Adder Using Adiabatic Logic.
|
Abstract |
| VLSI015 |
Hardware Design Of An Energy-Efficient High-Throughput Median Filter. |
Abstract |
| VLSI016 |
VLSI Implementation Of 3D Integer DCT For Video Coding Standards. |
Abstract |
| VLSI017 |
Low-Cost High-Performance VLSI Architecture For Montgomery Modular Multiplication. |
Abstract |
| VLSI018 |
Pre-Encoded Multipliers Based On Non-Redundant Radix-4 Signed-Digit Encoding. |
Abstract |
| VLSI019 |
Delay Efficient Error Detection And Correction Of Parallel IIR Filters Using VLSI Algorithms. |
Abstract |
| VLSI020 |
Addition Of Miller And Inverted Manchester Encoding Technique To Dedicated Short Range Communication With Full Hardware Utilization. |
Abstract |
| VLSI021 |
Analysis And Design Of Low-Power Reversible Carry Select Adder Using D-Latch. |
Abstract |
| VLSI022 |
A Modified Partial Product Generator For Redundant Binary Multipliers. |
Abstract |
| VLSI023 |
An Efficient VLSI Architecture For Data Encryption Standard And Its FPGA Implementation. |
Abstract |
| VLSI024 |
A Normal I/O Order Radix-2 FFT Architecture To Process Twin Data Streams For MIMO. |
Abstract |
| VLSI025 |
Design Of Delay Efficient Modified 16 Bit Wallace Multiplier. |
Abstract |
| VLSI026 |
Low Power Area Efficient Alu With Low Power Full Adder. |
Abstract |
| VLSI027 |
A Cellular Network Architecture With Polynomial Weight Functions. |
Abstract |
| VLSI028 |
Carry Speculative Adder With Variable Latency For Low Power VLSI.
| Abstract |
| VLSI029 |
A New VLSI Algorithm For A High-Throughput Implementation Of Type IV DCT. |
Abstract |
| VLSI030 |
Design And Implementation Of 64 Bit Multiplier Using Vedic Algorithm. |
Abstract |
| VLSI031 |
VLSI Architecture For Delay Efficient 32-Bit Multiplier Using Vedic Mathematic Sutras. |
Abstract |
| VLSI032 |
Delay Efficient Error Detection And Correction Of Parallel IIR Filters Using VLSI Algorithm. |
Abstract |
| VLSI033 |
A Modified Partial Product Generator For Redundant Binary Multipliers. |
Abstract |
| VLSI034 |
Low-Power and Area-Efficient Shift Register Using Recursive Approach to the
Design of a Parallel Self-Timed Adder.. |
Abstract |
| VLSI035 |
Design Of Fast FIR Filter Using Compressor And Carry Select Adder. |
Abstract |
| VLSI036 |
Design And Optimization Of 16×16 Bit Multiplier Using Vedic Mathematics. | .
Abstract |
| VLSI037 |
High Performance VLSI Architecture For 3-D Discrete Wavelet Transform. |
Abstract |
| VLSI038 |
Carry Speculative Adder With Variable Latency For Low Power VLSI. |
Abstract |
| VLSI039 |
Design Of High Speed Carry Select Adder Using Brent Kung Adder. |
Abstract |
| VLSI040 |
VLSI Implementation Of Boolean Algebra Based Cryptographic Algorithm. |
Abstract |
| VLSI041 |
Iterative Architecture AES For Secure VLSI Based System Design. |
Abstract |
| VLSI042 |
An Efficient VLSI Architecture For Discrete Hadamard Transform. |
Abstract |
| VLSI043 |
An Efficient VLSI Architecture For Data Encryption Standard And Its FPGA Implementation. |
Abstract |
| VLSI044 |
44. Low Power Array Multiplier Using Modified Full Adder. |
Abstract |
| VLSI045 |
A Single-Ended With Dynamic Feedback Control 8T Sub threshold SRAM Cell. |
Abstract |
| VLSI046 |
Low-Power Scan-Based Built-In Self-Test Based On Weighted Pseudorandom Test Pattern Generation And Reseeding. |
Abstract |
| VLSI047 |
Implementation Of Multiplier Architecture Using Efficient Carry Select Adders For Synthesizing FIR Filters. |
Abstract |
| VLSI048 |
Low-Power Parallel Chine Search Architecture Using A Two-Step Approach. |
Abstract |
| VLSI049 |
Memory-Reduced Turbo Decoding Architecture Using NII Metric Compression. |
Abstract |
| VLSI050 |
Input-Based Dynamic Reconfiguration Of Approximate Arithmetic Units For Video Encoding |
Abstract |
| VLSI051 |
High-Speed And Energy-Efficient Carry Skip Adder Operating Under A Wide Range Of supply Voltage Levels. |
Abstract |
| VLSI052 |
A Comparative Study Of FIR Filters Using Vedic And Booths Algorithm. |
Abstract |
| VLSI053 |
Hybrid LUT/Multiplexer FPGA Logic Architectures. |
Abstract |
| VLSI054 |
VLSI Architecture For Delay Efficient 32-Bit Multiplier Using Vedic Mathematic Sutras. |
Abstract |
| VLSI055 |
Low-Power And Area-Efficient Shift Register Using Pulsed Latches. |
Abstract |
| VLSI056 |
Scan Test Bandwidth Management For Ultra large-Scale System-On-Chip Architectures. |
Abstract |
| VLSI057 |
Fault Tolerant Parallel Filters Based On Error Correction Codes. |
Abstract |
| VLSI058 |
Low-Complexity Tree Architecture For Finding The First Two Minima. |
Abstract |
| VLSI059 |
Design Of Area And Delay Efficient Vedic Multiplier Using Carry Select Adder. |
Abstract |
| VLSI060 |
VLSI Computational Architectures For The Arithmetic Cosine Transform. |
Abstract |
| VLSI061 |
Aging-Aware Reliable Multiplier Design With Adaptive Hold Logic. |
Abstract |
| VLSI062 |
Fully Reused VLSI Architecture Of FM0/Manchester Encoding Using SOLS Technique For DSRC Applications. |
Abstract |
| VLSI063 |
A Novel Fault Detection And Correction Technique For Memory Applications. |
Abstract |
| VLSI064 |
An Efficient Binary Multiplier Design For High Speed Applications Using Karatsuba Algorithm And Urdhva- Tiryagbhyam Algorithm. |
Abstract |
| VLSI065 |
Flexible DSP Accelerator Architecture Exploiting Carry-Save Arithmetic. |
Abstract |
| VLSI066 |
A Generalized Algorithm And Reconfigurable Architecture For Efficient And Scalable Orthogonal Approximation Of DCT. |
Abstract |
| VLSI067 |
Optimized Designs Of Reversible Fault Tolerant BCD Adder And Fault Tolerant Reversible Carry Skip BCD Adder. |
Abstract |
| VLSI068 |
A Modified Partial Product Generator For Redundant Binary Multiplier. |
Abstract |
| VLSI069 |
Ocnoc: Efficient One-Cycle Router Implementation For 3D Mesh Network-On-Chip. |
Abstract |
| VLSI070 |
FPGA Implementation Of Efficient Vedic Multiplier. |
Abstract |
| VLSI071 |
An Optimized Modified Booth Recoder For Efficient Design Of The Add-Multiply Operator. |
Abstract |
| VLSI072 |
Fault Tolerant Parallel Ffts Using Error Correction Codes And Parseval Checks. |
Abstract |
| VLSI073 |
Multifunction Residue Architectures For Cryptography. |
Abstract |
| VLSI074 |
An Efficient Design Of 16 Bit MAC Unit Using Vedic Mathematics. |
Abstract |
| VLSI075 |
A Further Optimized Mix Column Architecture Design For The Advanced Encryption Standard. |
Abstract |
| VLSI076 |
Approximate Reverse Carry Propagate Adder For Energy-Efficient DSP Applications. |
Abstract |
| VLSI077 |
Architecture Optimization And Performance Comparison Of Nonce-Misuse-Resistant Authenticated Encryption Algorithms. |
Abstract |
| VLSI078 |
Low Power High Accuracy Approximate Multiplier Using Approximate High Order Compressors. |
Abstract |
| VLSI079 |
TOSAM:Anenergy-Efficienttruncation-Androunding-Basedscalableapproximate Multiplier. |
Abstract |
| VLSI080 |
Efficient Modular Adder Designs Based On Thermometer & One-Hot Encoding. |
Abstract |
| VLSI081 |
FPGA Based Implementation Of FIR Filter For FOFDM Waveform. |
Abstract |
| VLSI082 |
Design And Analysis Of Approximate Redundant Binary Multipliers. |
Abstract |
| VLSI083 |
Design Of Reversible Arithmetic Logic Unit With Built-In Testability. |
Abstract |
| VLSI084 |
A Combined Arithmetic-High-Level Synthesis Solution To Deploy Partial Carry-Save Radix-8 Booth Multipliers In Data path. |
Abstract |
| VLSI085 |
Ultra-Low-Voltage GDI-Based Hybrid Full Adder Design For Area And Energy-Efficient Computing Systems. |
Abstract |
| VLSI086 |
Low Power Approximate Unsigned Multipliers With Configurable Error Recovery. |
Abstract |
| VLSI087 |
A Two Speed Radix -4 Serial –Parallel Multiplier. |
Abstract |
| VLSI088 |
Performance Analysis Of Wallace Tree Multiplier With Kogge Stone Adder Using 15-4 Compressor. |
Abstract |
| VLSI089 |
Concurrent Error Detectable Carry Select Adder With Easy Testability. |
Abstract |
VLSI090 |
Design And Analysis Of Majority Logic Based Approximate Adders And Multipliers. |
Abstract |
VLSI091 |
Block-Based Carry Speculative Approximate Adder For Energy-Efficient Applications |
Abstract |
