| VLSI001 |
An Efficient Constant Multiplier Architecture Based on Vertical-Horizontal Binary Common Sub-expression Elimination Algorithm for Reconfigurable FIR Filter Synthesis |
Abstract |
| VLSI002 |
Low-cost and high-speed hardware implementation of contrast-preserving image dynamic range compression for full-HD video enhancement. |
Abstract |
| VLSI003 |
Low-Power and Area-Efficient Shift Register Using Pulsed Latches. |
Abstract |
| VLSI004 |
High-Throughput Digit-Level Systolic Multiplier Over GF (2m) Based on Irreducible Trinomials. |
Abstract |
| VLSI005 |
Aggressive Voltage Scaling Through Fast Correction of Multiple Errors with Seamless Pipeline Operation. |
Abstract |
| VLSI006 |
Aging-aware Reliable multiplier design with adaptive hold logic |
Abstract |
| VLSI007 |
A Low-Power Architecture for the Design of a One-Dimensional Median Filter |
Abstract |
| VLSI008 |
An Area- and Energy-Efficient FIFO Design Using
Error-Reduced Data Compression and Near-Threshold Operation for Image/Video Applications
|
Abstract |
| VLSI009 |
Efficient Parallel Architecture for Linear Feedback Shift Registers |
Abstract |
| VLSI010 |
Reconfigurable Filter Bank with Complete Control over Subband Bandwidths for Multi standard Wireless Communication Receivers |
Abstract |
| VLSI011 |
Result-Biased Distributed-Arithmetic-Based Filter Architectures for Approximately Computing the DWT |
Abstract |
| VLSI012 |
Vectored Implementation of Hierarchical 22n QAM |
Abstract |
| VLSI013 |
Area-Efficient Subquadratic Space-Complexity Digit-Serial Multiplier for Type-II Optimal Normal Basis of Using Symmetric TMVP and Block Recombination Techniques |
Abstract |
| VLSI014 |
Efficient VLSI Architecture for Decimation-in-Time
Fast Fourier Transform of Real-Valued Data
|
Abstract |
| VLSI015 |
Normalized Subband Adaptive Filtering Algorithm with Reduced Computational Complexity |
Abstract |
| VLSI016 |
A PFD and Charge Pump Switching Circuit to Optimize the Output Phase Noise of the PLL in 90 nm CMOS |
Abstract |
| VLSI017 |
Design and Analysis of an Adaptively Biased Low Dropout Regulator Using Enhanced Current Mirror Buffer |
Abstract |
| VLSI018 |
Design of Improved Performance Voltage Controlled Ring Oscillator |
Abstract |
| VLSI019 |
Analysis and Design of Dual-Mode CMOS LC-VCOs |
Abstract |
| VLSI020 |
Fully-Integrated Low-Dropout Regulator with Full-Spectrum Power Supply Rejection |
Abstract |
| VLSI021 |
Area Delay Efficient Binary Adders in QCA |
Abstract |
| VLSI022 |
Input vector monitoring concurrent BIST Architecture using SRAM cells |
Abstract |
| VLSI023 |
Area-delay-power efficient fixed point LMS Adaptive filter with low adaptation delay |
Abstract |
| VLSI024 |
Efficient FPGA Implementation of Addresses generator for WiMAX Deinterleaver |
Abstract |
| VLSI025 |
Low complexity Low Latency Architecture for matching of data encoded with hard systematic error correcting codes |
Abstract |
| VLSI026 |
Reverse converter design via parallel prefix adders: Novel components, methodology and implementations |
Abstract |
| VLSI027 |
Data Encoding Techniques for Reducing Energy Consumption in Network-on-Chip |
Abstract |
| VLSI028 |
Critical path analysis & low complexity implementation of the LMS adaptive algorithm
| Abstract |
